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A64S9316
Preliminary
Document Title 512K X 16 Bit Low Voltage Super RAMTM Revision History
Rev. No.
0.0 0.1
512K X 16 Bit Low Voltage Super RAMTM
History
Initial issue Add tASC, tAHC, tCEH, tWEH
Issue Date
May 16, 2002 July 31, 2002
Remark
Preliminary
PRELIMINARY
(July, 2002, Version 0.1)
AMIC Technology, Inc.
A64S9316
Preliminary
Features
n Operating voltage: 2.7V to 3.1V n Access times: 70 ns (max.) n Current: A64S9316 series: Operating: 35mA (max.) Power Down Standby: 10A (max.) n Fully SRAM compatible operation n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Industrial operating temperature range: -25C to +85C for -I n Available in 48-ball Mini BGA (6X8) package.
512K X 16 Bit Low Voltage Super RAMTM
General Description
The A64S9316 is a low operating current 8,388,608-bit Super RAM organized as 524,288 words by 16 bits and operates on low power supply voltage from 2.7V to 3.1V. It is built using AMIC's high performance CMOS DRAM process. Using hidden refresh technique, the A64S9316 provides a 100% compatible asynchronous interface. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. This A64S9316 is suited for low power application such as mobile phone and PDA or other battery-operated handheld device.
Pin Configuration
n Mini BGA (6X8) Top View 1 A B C D E F G H LB I/O8 I/O9 VSS VCC I/O14 I/O15 A18 2 OE 3 A0 A3 A5 A17 GND A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 VCC VSS I/O6 I/O7 NC
HB
I/O10 I/O11 I/O12 I/O13 NC A8
A64S9316G
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AMIC Technology, Inc.
A64S9316
Block Diagram
A0 8,388,608 MEMORY ARRAY
VCC VSS GND DECODER
A17 A18
I/O0 INPUT DATA CIRCUIT I/O7 COLUMN I/O INPUT DATA CIRCUIT
I/O8
I/O15
CE1 CE2 LB HB OE WE
CONTROL CIRCUIT
Pin Description
Symbol A0 - A18 CE1 CE2 I/O0 - I/O15 WE LB HB OE VCC VSS GND NC Address Inputs Chip Enable 1 Input Chip Enable 2 Input Data Input/Outputs Write Enable Input Byte Enable Input (I/O0 to I/O7) Byte Enable Input (I/O8 to I/O15) Output Enable Input Power Ground Ground No Connection Description
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A64S9316
Recommended DC Operating Conditions
(TA = 0C to + 70C or -25C to 85C) Symbol VCC VSS GND VIH VIL CL TTL Parameter Supply Voltage Ground Ground Input High Voltage Input Low Voltage Output Load Output Load Min. 2.7 0 0 2.4 -0.3 Max. 3.1 0 0 VCC + 0.3 +0.6 30 1 Unit V V V V V pF -
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V Storage Temperature, Tstg . . . . . . . . . -55C to +125C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W Soldering Temp. & Time . . . . . . . . . . . . 260C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics
Symbol Parameter
(TA = 0C to + 70C or -25C to 85C, VCC = 2.7V to 3.1V, GND = 0V) -70 Min. Max. 1 Min. -85 Max. 1 A VIN = GND to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC Min. Cycle, Duty = 100% CE1 = VIL, CE2 = VIH II/O = 0mA CE1 = VIL, CE2 = VIH VIH = VCC, VIL = 0V, f = 1MHz, II/O = 0mA Unit Conditions
ILI
Input Leakage Current Output Leakage Current
-
ILO
-
1
-
1
A
ICC1 Dynamic Operating Current ICC2
-
35
-
30
mA
-
5
-
5
mA
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AMIC Technology, Inc.
A64S9316
DC Electrical Characteristics (continued)
Symbol Parameter Min. Standby Power Supply Current Power Down Mode Standby Current Output Low Voltage Output High Voltage -70 Max. Min. -85 Max. CE1 VCC - 0.2V CE2 VCC - 0.2V VIN 0V CE2 0.2V IOL = 2.1mA IOH = -1.0mA Unit Conditions
ISB1
-
80
-
80
A A V V
ISB2 VOL VOH
2.4
10 0.4 -
2.4
10 0.4 -
Truth Table
CE1
CE2 H H L
OE X X X
WE X X X
LB X H X L
HB X H X L H L L H L X
I/O0 to I/O7 Mode Not selected Not selected Not selected Read Read High - Z Write Write Not Write/Hi - Z High - Z High - Z
I/O8 to I/O15 Mode Not selected Not selected Not selected Read High - Z Read Write Not Write/Hi - Z Write High - Z High - Z
VCC Current ISB1, ISB ISB1, ISB ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2
H X X
L
H
L
H
L H L
L
H
X
L
L H
L
H
H
H
X
Note: X = H or L
Capacitance (TA = 25C, f = 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 10 10 Unit pF pF Conditions VIN = 0V VI/O = 0V
* These parameters are sampled and not 100% tested.
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AMIC Technology, Inc.
A64S9316
Initialization
The A64S9316 is initialized in the power-on sequence according to the following. 1. To stabilize internal circuits, after turning on the power, a 350s or longer wait time must precede any signal toggling. 2. After the wait time, it can be normal operation.
Power on Chart
VCC(min) VCC
CE1
50ns (min) 350us Wait Time Normal Operation
CE2
Notes: 1. Following power application, make CE2 and CE1 high level during the wait time interval. 2. After power on sequence, the normal operating CE2 must keep at high.
Power on / Depower down State Machine
Power on CE1=V IH, CE2=V IH Wait 350us Initial State CE1=V IL, CE2=V IH CE1=V IH, CE2=V IH CE1=V IH, CE2=V IH CE1=V IL, CE2=V IH Standby Mode CE1=V IH CE2=V IL, Power Down Mode Active CE1=V IH CE2=V IL,
CE1=V IH CE2=V IH,
Standby Mode Characteristics
Standby Mode Standby Power down Memory Cell Data Hold Valid Invalid Standby Supply Current (A) 100 (ISB1) 10 (ISB2)
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A64S9316
Avoid Timing
Following figures are show you an abnormal timing which is not supported on Super RAM and their solution. At normal operation, if your system have a timing which sustain invalid states over 10s at normal mode like Figure 1. There are some guide line for proper operation of Super RAM. When your system have multiple invalid address signal shorter than tRC on the timing which showed in Figure 1, Super RAM need toggle the CE1 to "high" about "tRC" (Figure 2).
CE1 Less than t RC
Over 10us
Address
Figure 1
toggle CE1 to high every 10us 10us CE1 70ns
Address
Figure 2
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A64S9316
AC Characteristics (TA = 0C to +70C or -25C to 85C, VCC = 2.7V to 3.1V)
Symbol Parameter Min. Read Cycle tRC tSKEW tAA tACE tBE tOE tCLZ tBLZ tOLZ tCHZ tBHZ tOHZ tOH tASC tAHC tCEH Write Cycle tWC tSKEW tCW tBW tAS tAW tWP tWR tWHZ tDW tDH tOW tASC tAHC tCEH tWEH Write Cycle Time Address Skew Chip Enable to End of Write Byte Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write Address Setup to CE1 Low Address Hold Time from CE1 High CE1 High Pulse With WE High Pulse With 70 60 60 0 60 50 0 30 0 5 0 0 10 10 10 20 85 70 70 0 70 55 0 35 0 5 0 0 10 10 10 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address Skew Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Byte Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Byte Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change Address Setup to CE1 Low Address Hold Time from CE1 High CE1 High Pulse With 70 10 5 5 0 0 0 10 0 0 10 10 70 70 70 35 25 25 25 85 10 5 5 0 0 0 10 0 0 10 10 85 85 85 45 35 35 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -70 Max. Min. -85 Max. Unit
Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
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AMIC Technology, Inc.
A64S9316
Timing Waveforms
Read Cycle 1
(1, 2, 4, 6)
tSKEW
tRC
tSKEW
tRC
Address
tAA
tOH
tAA
tOH
DOUT
tASC
CE1
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AMIC Technology, Inc.
A64S9316
Read Cycle 2-1
(1, 3, 6)
tSKEW
tRC
tRC
tSKEW
Address
tASC tAA tCEH tAHC tASC tAA tAHC
CE1
tACE tCLZ 5 tCHZ 5
tBE tACE tCLZ 5 tBE tCHZ 5
HB , LB
tBE
tBLZ 5
tBHZ 5
tBLZ 5
tBHZ 5
OE
tOE tOLZ 5 tOHZ 5 tOE tOLZ 5 tOHZ 5
DOUT
Read Cycle 2-2
(1, 3, 6)
tSKEW
tRC
tSKEW
tRC
tSKEW
Address
tASC tAA tAA tAHC
CE1
tACE tCLZ 5 tCHZ 5 tBE
HB , LB
tBE
tBLZ 5
tBHZ 5
tBLZ 5
tBHZ 5
OE
tOE tOLZ 5 tOHZ 5 tOE tOLZ 5 tOHZ 5
DOUT
Notes:
1. WE is high for Read Cycle. 2. Device is continuously enabled CE1 = VIL, HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE1 and ( HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high for Read Cycle.
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A64S9316
Timing Waveforms (continued)
Write Cycle 1-1 (Write Enable Controlled)
tSKEW tWC tWC tSKEW
(6)
Address
tASC tAW tCW tCEH tAHC tASC tAW tCW tAHC
CE1
tBW tBW
HB , LB
tAS 1 tWP2 tWR 3 tAS 1 tWP2 tWR 3
WE
tDW tDH tDW tDH
Data In
tWHZ 4 tOW tWHZ 4 tOW
Data Out
Write Cycle 1-2 (Write Enable Controlled)
tSKEW tWC tSKEW tWC tSKEW
(6)
Address
tASC tAHC
CE1
tBW tBW
HB , LB
tAS 1 tWP2 tWR3 tAS 1 tWP2 tWEH tDW tDH tDW tDH tWR 3
WE
Data In
tWHZ 4 tOW tWHZ 4 tOW
Data Out
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AMIC Technology, Inc.
A64S9316
Timing Waveforms (continued)
Write Cycle 2-1 (Chip Enable Controlled)
tSKEW tWC tWC tSKEW
(6)
Address
tAW tASC tCW 2 tAHC tASC tCEH tCW 2 tAW tAHC
CE1
tBW tWR 3 tBW tWR 3
HB , LB
tWP tWP
WE
tDW tDH tDW tDH
Data In
tWHZ 4 tOW tWHZ 4 tOW
Data Out
Write Cycle 2-2 (Chip Enable Controlled)
tSKEW tWC tSKEW tWC tSKEW
(6)
Address
tAW tASC tAHC
CE1
tBW tWR 3 tBW tWR 3
HB , LB
tWP tWP
WE
tDW tDH tDW tDH
Data In
tWHZ 4 tOW tWHZ 4 tOW
Data Out
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AMIC Technology, Inc.
A64S9316
Timing Waveforms (continued)
Write Cycle 3-1 (Byte Enable Controlled)
tSKEW tWC tWC tSKEW
(6)
Address
tAW tASC tCW tAHC tASC tCEH tCW tAW tAHC
CE1
tAS 1 tBW 2 tWR 3 tAS 1 tBW 2 tWR 3
HB , LB
tWP tWP
WE
tDW tDH tDW tDH
Data In
tWHZ 4 tOW tWHZ 4 tOW
Data Out
(6)
Write Cycle 3-2 (Byte Enable Controlled)
tSKEW tWC tSKEW tWC tSKEW
Address
tASC tAW tAHC
CE1
tAS 1 tBW 2 tWR 3 tAS 1 tBW 2 tWR 3
HB , LB
tWP tWP
WE
tDW tDH tDW tDH
Data In
tWHZ 4 tOW tWHZ 4 tOW
Data Out
Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP, tBW) of a low CE1, WE and ( HB and, or LB ). 3. tWR is measured from the earliest of CE1 or WE or ( HB and, or LB ) going high to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high for Write Cycle.
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AMIC Technology, Inc.
A64S9316
AC Test Conditions
Input Pulse Levels Input Rise And Fall Time Input and Output Timing Reference Levels Output Load 0.4V to 2.4V 5 ns 1.5V See Figures 3 and 4
TTL
TTL
CL 30pF
CL 5pF
* Including scope and jig.
* Including scope and jig.
Figure 3. Output Load
Figure 4. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW
Ordering Information
Operating Current Max. (mA) Power Down Mode Standby Current Max. (A) 10 10 10 10
Part No.
Access Time (ns)
Package
A64S9316G-70 A64S9316G-85 A64S9316G-70I A64S9316G-85I
70 85 70 85
35 30 35 30
48B Mini BGA 48B Mini BGA 48B Mini BGA 48B Mini BGA
Note: -I is for industrial operating temperature range
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A64S9316
Package Information Mini BGA 6X8 (48 BALLS) Outline Dimensions
unit : millimeter(mm)
Bottom View Pin A1 Index 654 321 Pin A1 Index
Top View
C1
E F G H
A
A B1 Diameter D Solder Ball
B
D
Symbol A B B1 C C1 D E E1 E2
Min 5.90 7.90 0.30 1.00 0.2
Typ 0.75 6.00 3.75 8.00 5.25 0.35 1.10 0.36 0.25
Max 6.10 8.10 0.40 1.20 0.3
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AMIC Technology, Inc.
C E2 E
A B C D
0.10 E1

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